psort: sistema di documentazione

L'elaborato presenta alcune applicazioni pratiche della documentazione di un software (nello specifico nel progetto psort). In particolare fornisce delle guide rapide per l'utilizzo di Doxygen e la creazione di una man pageopenEmbarg

Travel, modernity and rural landscapes in nineteenth century Liguria

New roads and later railways were essential for the modernisation and rapid economic development of North-western Italy in the early nineteenth century. The new routes also encouraged an increasing number of foreign travellers to visit the region. They opened up fresh tracts of countryside and provided novel viewpoints and points of interest; many travellers took the opportunity to record these views with topographical drawings and watercolours. In this paper we make use of some of these views to examine how the modernized transport routes released new places to be celebrated by tourists and became themselves features and objects of especial interest and comment. We examine the works of three artists, one English and two Italian, who depicted landscapes of contrasting rural Ligurian landscapes. Their drawings and prints are contextualised and interpreted with maps, field data, archival documents and contemporary descriptions of roads and railways by travellers and in guidebooks

Studio ed applicazione delle tecniche di Real Number Modeling e Assertion Based Verification al progetto di circuiti mixed-signal. Study and application of Real Number Modeling and Assertion Based Verification techniques to mixed-signal circuit design

Per primo si è realizzato uno studio del Real Number Modeling. Esso mira a sostituire i blocchi analogici presenti in un circuito Mixed-Signal con modelli realizzati attraverso linguaggi HDL, al fine di emulare la funzionalità di un intero dispositivo in simulatori ad eventi tipicamente digitali. L'elaborato comprende anche esempi di applicazione in VHDL. Si analizza inoltre l'Assertion Based Verification in Mixed-Signal e come implementare le asserzioni analogiche in SystemVerilog Assertio